Efficient RAS support for 3D Die-Stacked DRAM

Die-stacked DRAM is one of the most promising memory architectures to satisfy high bandwidth and low latency needs of many computing systems. But, with technology scaling, all memory devices are expected to experience significant increase in single and multi-bit errors. 3D die-stacked DRAM will have the added burden of protecting against single through-siliconvia (TSV) failures, which translate into multiple bit errors in a single cache line, as well multiple TSV failures that may lead to an entire channel failure. To exploit wide I/O capability of 3D DRAM, large chunks of data are laid out contiguously in a single channel and an entire cache line is sourced from a single channel. Conventional approaches such as ECC DIMM and chipkill-correct are inefficient since they spread data across multiple DRAM layers to protect against failures and also place restrictions on the number of memory layers that must be protected together. This paper adapts several well known error detection and correction techniques while taking into account 3D DRAM’s unique organization. First, we decouple error correction from detection and perform error detection using a novel two level 8-bit interleaved parity to handle diestacked DRAM-specific failure modes such as TSV failures. We then adapt RAID5-like parity, a technique developed for hard disks which also layout large chunks of data contiguously, for recovering from a wide range of errors from single-bit errors to channel-level failures without the need to splice data across multiple layers. As further optimizations, a two-step decoupled error correction code update process is used to improve write speed, and an error detection code cache is used for improving read/write performance without compromising reliability. The proposed approaches effectively reduce the FIT rate with 15.7% area and almost negligible performance overhead.